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2025, 06, v.62 26-32
面向10 k V以上碳化硅器件耐压区厚外延技术研究
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DOI: 10.13250/j.cnki.wndz.25060201
摘要:

随着10 k V及以上超高压碳化硅(Si C)功率器件在柔性输电等领域的需求增长,开发低位错、低缺陷密度、长少子寿命的厚外延材料成为关键挑战,是当前Si C材料研究的核心问题。基于单片水平式Si C外延设备,通过引入双界面调制缓冲层外延生长技术,成功实现了对缓冲层与衬底及漂移层之间界面应力的调控,显著降低了外延片基平面位错密度,结合漂移层生长速率、缓冲层工艺以及C/Si比的协同优化,显著提升了4H-Si C厚外延材料的性能。实验结果表明:优化后的缓冲层工艺通过渐变掺杂设计有效调控界面应力,将基平面位错密度从1.5 cm-2降至0.07 cm-2;同时,通过将生长速率提升至70μm/h并优化C/Si比至0.85,成功制备了厚度100μm、掺杂浓度2.5×1014cm-3的高质量外延层,原生少子寿命均值达1.76μs,材料均匀性及表面缺陷密度均满足10 kV以上超高压器件耐压区需求。

Abstract:

With the increasing demands for 10 kV andhigher ultra-high voltage silicon carbide(SiC)power devices in fields such as flexible power transmission,the development of thick epitaxial materials with low dislocation,low defect density and long minority carrier lifetime has become a critical challenge,representing a core issue in current SiC material research.Based on single-wafer horizontal SiC epitaxial equipment,interface stress regulation between buffer layers and substrate/drift layers was successfully achieved through implementation of dual-interface modulated buffer layer epitaxial growth technology,which significantly reduces basal plane dislocation density in epitaxial wafers.Through synergistic optimization of drift layer growth rate,buffer layer processes,and C/Si ratio,the performance of 4H-SiC thick epitaxial materials is remarkably enhanced.Experimental results demonstrate that the optimized buffer layer process effectively modulates interface stress through graded doping design,reducing basal plane dislocation density from 1.5 cm-2 to 0.07 cm-2.Simultaneously,by increasing growth rate to 70 μm/h and optimizing C/Si ratio to 0.85,high-quality epitaxial layers with 100 μm thickness and doping concentration of 2.5×1014 cm-3 was successfully fabricated.The average native minority carrier lifetime reaches 1.76 μs,with material uniformity and surface defect density meeting the requirements for voltage-resistant regions in 10 k V andhigher ultra-high voltage devices.

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基本信息:

DOI:10.13250/j.cnki.wndz.25060201

中图分类号:TN304.24

引用信息:

[1]房玉龙,李帅,芦伟立等.面向10 k V以上碳化硅器件耐压区厚外延技术研究[J].微纳电子技术,2025,62(06):26-32.DOI:10.13250/j.cnki.wndz.25060201.

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