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在4°斜切的6英寸(1英寸=2.54 cm)4H-SiC衬底上生长了约12μm厚的同质外延层，利用化学机械抛光(CMP)的方法对外延层进行逐层剥离。通过光致发光(PL)测试观察Σ形基平面位错(BPD)在外延层中的位置及深度分布。对同晶体临近衬底进行KOH腐蚀，使用光学显微镜观察并统计了衬底中BPD密度。结合衬底平整度测试，分析了外延层中高密度BPD的形成原因。最后，在CMP后残留了2.53μm厚外延层的晶圆上进行了相同掺杂浓度的二次外延，并对晶圆进行PL测试并观察BPD的变化情况。结果表明，BPD在衬底上方接近3μm的位置滑移成核，衬底中BPD的密度是影响外延层中Σ形BPD数量的主要因素。晶圆翘曲度会在一定程度上影响温度梯度，从而对BPD的形成产生影响。因此，控制衬底中心区域的BPD密度和晶圆翘曲度有助于减少Σ形BPD的形成，进而有助于提高SiC器件的性能和可靠性。
Abstract：A homoepitaxial layer with about 12 μm thickness was grown on a 4° off-axis 6-inch(1 inch=2.54 cm) 4H-SiC substrate, and the epitaxial layer was sequentially peeled off using chemical mechanical polishing(CMP). The position and depth distribution of Σ-shaped basal plane dislocations(BPDs) in the epitaxial layer were observed by photoluminescence(PL) test. KOH etching was carried out on the adjacent substrate of the same crystal, and the density of BPD in the substrate was observed and counted by optical microscope. Combined with the substrate flatness test, the formation reason of high-density BPD in epitaxial layer was analyzed. Finally, the second epitaxial growth with the same doping concentration was performed on wafers retaining a 2.53 μm-thick epitaxial layer after CMP, followed by PL testing and observation of variations in BPDs, and the wafer was subjected to PL test to observe the change of BPDs. The results show that the BPD slippage nucleation at a position close to 3 μm above the substrate, and the density of BPD in the substrate is the main reason that affects the number of Σ-shaped BPD in the epitaxial layer. The warpage of the wafer will affect the temperature gradient to a certain extent, which will have an impact on the formation of BPD. Therefore, controlling the BPD density in the central region of the substrate and wafer warpage can help to reduce the formation of Σ-shaped BPD, thereby it helps to improve the performance and reliability of SiC devices.
[1] OKUMURA H.Presentstatus and future prospect of widegap semiconductor high-power devices [J].Japanese Journal of Applied Physics,2006,45(10A):7565.
[2] KIMOTO T.Material science and device physics in SiC technology for high-voltage power devices [J].Japanese Journal of Applied Physics,2015,54(4):040103.
[3] TSUCHIDA H,KAMATA I,MIYAZAWA T,et al.Recent advances in 4H-SiC epitaxy for high-voltage power devices [J].Materials Science in Semiconductor Processing,2018,78:2-12.
[4] BERGMAN J P,LENDENMANN H,NILSSON P ?,et al.Crystal defects as source of anomalous forward voltage increase of 4H-SiC diodes [J].Materials Science Forum,2001,353/354/355/356:299-302.
[5] CALDWELL J D,STAHLBUSH R E,IMHOFF E A,et al.Recombination-induced stacking fault degradation of 4H-SiC merged-PiN-Schottky diodes [J].Journal of Applied Phy-sics,2009,106(4):044504.
[6] BU Y,YOSHIMOTO H,WATANABE N,et al.Fabrication of 4H-SiC PiN diodes without bipolar degradation by improved device processes [J].Journal of Applied Physics,2017,122(24):244504.
[7] LAI L L,CUI Y X,ZHONG Y,et al.Impacts of silicon carbide defects on electrical characteristics of SiC devices [J].Journal of Applied Physics,2025,137(6):060701.
[8] HA S,MIESZKOWSKI P,SKOWRONSKI M,et al.Dislocation conversion in 4H silicon carbide epitaxy [J].Journal of Crystal Growth,2002,244(3/4):257-266.
[9] ZHANG X,SKOWRONSKI M,LIU K X,et al.Glide and multiplication of basal plane dislocations during 4H-SiC homoepitaxy [J].Journal of Applied Physics,2007,102(9):093520.
[10] NAGANO M,TSUCHIDA H,SUZUKI T,et al.Annealing induced extended defects in as-grown and ion-implanted 4H-SiC epitaxial layers [J].Journal of Applied Physics,2010,108(1):013511.
[11] WANG H,DUDLEY M,WU F,et al.Studies of the origins of half-loop arrays and interfacial dislocations observed in homoepitaxial layers of 4H-SiC [J].Journal of Electronic Materials,2015,44(5):1268-1274.
[12] ZHANG Z,SUDARSHAN T S.Basal plane dislocation-free epitaxy of silicon carbide [J].Applied Physics Letters,2005,87(15):151913.
[13] MAHADIK N A,STAHLBUSH R E,IMHOFF E A,et al.Mitigation of BPD by pre-epigrowth high temperature substrate annealing [J].Materials Science Forum,2016,858:233-236.
[14] STAHLBUSH R E,VANMIL B L,MYERS-WARD R L,et al.Basal plane dislocation reduction in 4H-SiC epitaxy by growth interruptions [J].Applied Physics Letters,2009,94(4):041916.
[15] HORI T,DANNO K,KIMOTO T.Fast homoepitaxial growth of 4H-SiC with low basal-plane dislocation density and low trap concentration by hot-wall chemical vapor deposition [J].Journal of Crystal Growth,2007,306(2):297-302.
[16] WADA K,TERAO T,ITOH H,et al.99.9% BPD free 4H-SiC epitaxial layer with precisely controlled doping upon 3×150 mm hot-wall CVD [J].Materials Science Forum,2018,924:72-75.
[17] 郭钰，刘春俊，张新河，等.碳化硅同质外延质量影响因素的分析与综述 [J].人工晶体学报，2024,53(2):210-217.GUO Y,LIU C J,ZHANG X H,et al.Analysis and review of influencing factors of SiC homo-epitaxial wafers quality [J].Journal of Synthetic Crystals,2024,53(2):210-217(in Chinese).
[18] 杨龙，赵丽霞，吴会旺.4H-SiC同质外延基面位错的转化 [J].微纳电子技术，2020,57(3):250-254.YANG L,ZHAO L X,WU H W.Conversion of basal plane dislocations during 4H-SiC homo-epitaxy [J].Micronanoelectronic Technology,2020,57(3):250-254 (in Chinese).
[19] NA M,BAHNG W,JANG H,et al.Effects of stress on the evolution of Σ-shaped dislocation arrays in a 4H-SiC epitaxial layer [J].Journal of Applied Physics,2021,129(24):245101.
[20] MAHADIK N A,STAHLBUSH R E,SUNG W.Formation mechanism of horizontal-half-loop arrays and stacking fault expansion behavior in thick SiC epitaxial layers [J].Journal of Applied Physics,2022,131(22):225702.
[21] FUJIE F,SHIONO T,MURATA K,et al.Formation of basal plane dislocations by stress near epilayer/substrate interface of large-diameter SiC wafers with thick epitaxial layers [J].Journal of Applied Physics,2024,135(23):235706.
[22] LI Z,ZHANG X,ZHANG Z H,et al.Microstructure of interfacial basal plane dislocations in 4H-SiC epilayers [J].Materials Science Forum,2019,954:77-81.
[23] HA S,CHUNG H J,NUHFER N T,et al.Dislocation nucleation in 4H silicon carbide epitaxy [J].Journal of Crystal Growth,2004,262(1/2/3/4):130-138.
[24] ZHANG N,CHEN Y,ZHANG Y,et al.Nucleation mechanism of dislocation half-loop arrays in 4H-silicon carbide homoepitaxial layers [J].Applied Physics Letters,2009,94(12):122108.
[25] WANG H H,WU F Z,YANG Y,et al.Studies of relaxation processes and basal plane dislocations in CVD grown homoepitaxial layers of 4H-SiC [J].ECS Transactions,2014,64(7):213-222.
[26] TSUCHIDA H,KAMATA I,KOJIMA K,et al.In-fluence of growth conditions and substrate properties on formation of interfacial dislocations and dislocation half-loop arrays in 4H-SiC(0001) and (000-1) epitaxy [J].MRS Online Proceedings Library,2008,1069(1):10690403.
基本信息:
DOI：10.13250/j.cnki.wndz.25070302
中图分类号:TN304.24
引用信息:
[1]尹浩田,薛宏伟,吴会旺等.4H-SiC外延层高密度Σ形基平面位错成因研究[J].微纳电子技术,2025,62(07):44-50.DOI:10.13250/j.cnki.wndz.25070302.
基金信息: