| 1,460 | 2 | 135 |
| 下载次数 | 被引频次 | 阅读次数 |
集成电路在后摩尔时代的发展呈现出多模式创新的特点。综述了后摩尔时代中两大创新发展热点，即鳍式场效应晶体管/环绕栅场效应晶体管(FinFET/GAAFET)纳电子学和基于深度学习新算法的人工智能(AI)芯片，并介绍了其发展历程和近两年的最新进展。在FinFET/GAAFET纳电子学领域，综述并分析了当今Si基CMOS集成电路的发展现状，包含Intel的IDM模式、三星和台积电的代工模式3种技术路线，及其覆盖了22、14、10、7和5 nm集成电路纳电子学的5代技术各自的创新特点，以及未来3和2 nm技术节点GAAFET的各种创新结构的前瞻性技术研究。摩尔定律的继续发展将以Si基FinFET和GAAFET的技术发展为主。在AI芯片领域，综述并分析了数字AI芯片和模拟AI芯片的发展现状，包含神经网络云端和边缘计算应用的处理器(图像处理器(GPU)、张量处理器(TPU)和中央处理器(CPU))、加速器和神经网络处理器(NPU)等的计算架构的创新，各种神经网络算法和计算架构结合的创新，以及基于存储中计算新模式的静态随机存取存储器(SRAM)和电阻式随机存取存储器(RARAM)的创新。人工智能芯片的创新发展可弥补后摩尔时代集成电路随晶体管密度上升而计算能力增长缓慢的不足。
Abstract：The development of integrated circuits in the post-Moore era presents the characteristics of multimodal innovation. Two great innovation and development hots in the age of post-Moore are reviewed: fin field-effect transistor/gate all around field-effect transistor(FinFET/GAAFET) nanoelectronics and artificial intelligence(AI) chips based on the new algorithm of deep learning, and their development and the latest progress over the last two years are introduced. In the field of FinFET/GAAFET nanoelectronics, the current development status of Si-based CMOS integrated circuits(ICs) is reviewed and analyzed, including three technical routes about the IDM model of Intel, the foundry patterns of Samsung and TSMC, and their own innovative features covered the five-generation IC nanoelectronics technology on 22, 14, 10, 7 and 5 nm, and the forward-looking technology research about various innovative structures of GAAFET in 3 and 2 nm technology nodes in the future. The continued development of Moore's law will be dominated by the technological development of Si-based FinFET and GAAFET. In the field of AI chips, the current development of the digital AI chips and the analog AI chips are reviewed and analyzed, including the innovation on computing architectures of processors such as graphic processing unit(GPU),tensorflow processing unit(TPU) and central processing unit(CPU) in neural network cloud and edge computing applications, accelerators and NPU, the innovation of all kinds of neural network algorithms combined with computing architectures, and the innovation of static random-access memory(SRAM) and resistive random-access memory(RARAM) based on the new model of computing in the memory. The innovative development of AI chips can make up for the shortcomings of computing power slow growth of integrated circuits in the post-Moore era as transistor density increases.
[1] JAN C H,BHATTACHARYA U,BRAIN R,et al.A 22 nm SoC platform technology featuring 3D tri-gate and high-k/metal gate,optimized for ultra low power,high performance and high density SoC applications [C]// Procee-dings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2012:3.1.1-3.1.4.
[2] NATARAJAN S,AGOSTINELLI M,AKBAR S,et al.A 14 nm logic technology featuring 2nd-generation FinFET transistors,air-gapped interconnects,self-aligned double patterning and a 0.058 8 m2 SRAM cell size [C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2014:3.7.1-3.7.3.
[3] AUTH C,ALIYARUKUNJU A,ASORO M,et al.A 10 nm high performance and low power CMOS technology featuring 3rd generation FinFET transistor,self-aligned quad patterning,contact over active gate and cobalt local interconnects[C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2017:673-676.
[4] Intel火力全开：2024开启埃米时代 2025或用下一代光刻机“反超台积电”[EB/OL].(2021-07-27) [2021-09-08].https://www.cnbeta.com/articles/tech/1158477.htm.
[5] WU S Y,LIN C Y,CHIANG M C,et al.A 16 nm FinFET CMOS technology for mobile SoC and computing applications[C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).Washington,USA,2013:224-227.
[6] WU S Y,LIN C Y,CHIANG M C,et al.Demonstration of a sub-0.03 μm2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10 nm node[C]//Proceedings of IEEE Symposium on VLSI Technology.Honolulu,USA,2016:7573390-1-7573390-2.
[7] WU S Y,LIN C Y,CHIANG M C,et al.A 7 nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027 μm2 high density 6-T SRAM cell for mobile SoC applications[C]//Proceedings of IEEE Interna-tional Electron Devices Meeting (IEDM).San Francisco,USA,2016:43-46.
[8] YEAP G,LIN S S,CHEN Y M,et al.5 nm CMOS production technology platform featuring full-fledged EUV,and high mobility channel FinFETs with densest 0.021 μm2 SRAM cells for mobile SoC and high performance computing applications [C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2019:879-882.
[9] CHANG J T,CHEN Y H,CHAN G,et al.A 5 nm 135 Mb SRAM in EUV and high-mobility-channel FinFET technology with metal coupling and charge-sharing write-assist circuitry schemes for high-density and low-VMIN applications [C]//Proceedings of IEEE International Solid-State Circuits Conference.San Francisco,USA,2020:238-239.
[10] CHEN W C,WEN C H,FU C M,et al.A 4-to-18 GHz active poly phase filter quadrature clock generator with phase error correction in 5 nm CMOS [C]//Proceedings of IEEE Symposium on VLSI Circuits.Honolulu,USA,2020:9162794-1-9162794-2.
[11] 全球首个7 nm芯麒麟980国内已亮相，华为Mate20率先搭载最快10月[EB/OL].(2019-03-05) [2021-09-08].https://t.cj.sina.com.cn/articles/view/6499459229/18365e09d00100bwcm?from=tech.
[12] 唯一一家有2款7 nm芯片手机品牌，华为发布麒麟810[EB/OL].(2019-06-21) [2021-09-08].https://news.sina.com.cn/o/2019-06-21/doc-ihytcitk6788456.shtml.
[13] 来了!华为5 nm麒麟9000系列芯片曝光：还有9000E[EB/OL].(2020-09-08)[2021-09-08].https://www.sohu.com/a/417085355_116157.
[14] 3 nm来了!台积电：一个能打的够没有![EB/OL].(2020-08-26) [2021-09-08].https://news.zol.com.cn/751/7511979.html.
[15] SEO K I,HARAN B,GUPTA D,et al.A 10 nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI [C]//Proceedings of Sympo-sium on VLSI Technology (VLSI-Technology):Digest of Technical Papers.Honolulu,USA,2014:6894322-1-6894322-2.
[16] CHO H J,OH H S,NAM K J,et al.SiFinFET based 10 nm technology with multi Vt gate stack for low power and high performance applications [C]//Proceedings of IEEE Symposium on VLSI Technology.Honolulu,USA,2016:7573359-1-7573359-2.
[17] XIE R,MONTANINI P,AKARVARDAR K,et al.A 7 nm FinFET technology featuring EUV patterning and dual strained high mobility channels [C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2016:47-50.
[18] HA D,YANG C,LEE J,et al.Highly manufacturable 7 nm FinFET technology featuring EUV lithography for low power and high performance applications [C]//Proceedings of IEEE Symposium on VLSI Technology.Kyoto,Japan,2017:68-69.
[19] JEONG J H,KO Y G,SON K W,et al.Performance-power management aware state-of-the-art 5 nm FinFET design(5LPE) with dual CPP from mobile to HPC application[C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2020:405-408.
[20] BAECK S,LEE I,TANG H,et al.5 nm low power SRAM featuring dual-rail architecture with voltage-tracking assist circuit for 5G mobile application [C]//Proceedings of IEEE Symposium on VLSI Circuits Digest of Technical.Kyoto,Japan,2021:9492168-1-9492168-2.
[21] 三星5 nm芯片生产线开建[EB/OL].(2020-05-25) [2021-09-08].https://www.21ic.com/article/750779.html.
[22] 高通：骁龙888将由三星5 nm独家代工比台积电更适合[EB/OL].(2020-12-03) [2021-09-08].http://www.elecfans.com/d/1404716.html.
[23] MERTENS H,RITZENTHALER R,HIKAVYY A,et al.Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates[C]//Proceedings of IEEE Sympo-sium on VLSI Technology.Honolulu,USA,2016:7573416-1-7573416-2.
[24] LOUBET N,HOOK T,MONTANINI P,et al.Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET[C]//Proceedings of IEEE Symposium on VLSI Technology.Kyoto,Japan,2017:7998183-1-7998183-2.
[25] WECKX P,RYCKAERT J,PUTCHA V,et al.Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3 nm [C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2017:505-508.
[26] BAE G,BAE D I,KANG M,et al.3 nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications[C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2018:656-659.
[27] JOUNG S,KIM S.Leakage performance improvement in multi-bridge-channel field effect transistor(MBCFET) by adding core insulator layer[C]//Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).Udine,Italy,2019:8870498-1-8870498-4.
[28] WECKX P,RYCKAERT J,DENTONI LITTA E,et al.Novel forksheet device architecture as ultimate logic scaling device towards 2 nm [C]//Proceedings of IEEE International Electron Devices Meeting (IEDM).San Francisco,USA,2019:871-874.
[29] 台积电2 nm工艺重大突破 2023年风险试产良率或达90%[EB/OL].(2020-09-22)[2021-09-08].https://finance.sina.cn/tech/2020-09-22/detail-iivhuipp5854891.d.html?fromtech=1.
[30] 全球首款2纳米制程芯片问世：每平方毫米3.3亿晶体管，IBM打造[EB/OL].(2021-05-07) [2021-09-08].https://finance.sina.com.cn/tech/2021-05-07/doc-ikmyaawc3875973.shtml.
[31] RYCKAERT J,SCHUDDINCK P,WECKX P,et al.The complementary FET (CFET) for CMOS scaling beyond N3 [C]//Proceedings of IEEE Symposium on VLSI Technology.Honolulu,USA,2018:141-142.
[32] SCHUDDINCK P,ZOGRAFOS O,WECKX P,et al.Device-,circuit- & block-level evaluation of CFET in a 4 track library [C]//Proceedings of IEEE Symposium on VLSI Technology.Kyoto,Japan,2019:204-205.
[33] CHENG C K,HO C T,LEE D,et al.A routability-dri-ven complimentary-FET (CFET) standard cell synthesis framework using SMT[C]//Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD).San Diego,USA,2020:9256570-1-9256570-8.
[34] SUBRAMANIAN S,HOSSEINI M,CHIARELLA T,et al.First monolithic integration of 3D complementary FET (CFET) on 300 mm wafers [C]//Proceedings of IEEE Symposium on VLSI Technology.Honolulu,USA,2020:9265073-1-9265073-2.
[35] VINCENT B,ERVIN J,BOEMMELS J,et al.A benchmark study of complementary-field effect transistor (CFET) process integration options:comparing bulk vs.SOI vs.DSOI starting substrates [C]//Proceedings of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference.San Jose,USA,2019:9320683-1-9320683-2.
[36] DASH T P,DEY S,JENA J,et al.Metal grain granula-rity induced variability in gate-all-around Si-nanowire transistors at 1 nm technology node[C]//Proceedings of Devices for Integrated Circuit (DevIC).Kalyani,India,2019:286-290.
[37] MOROZ V,LIN X W,ASENOV P,et al.Can we ever get to a 100 nm tall library?power rail design for 1nm technology node [C]//Proceedings of IEEE Symposium on VLSI Technology.Honolulu,USA,2020:9265022-1-9265022-2.
[38] HENNESSY J L,PATTERSON D A.A new golden age for computer architecture [J].Communications of the ACM,2019,62 (2):48-60.
[39] LUEBKE D,HARRIS M,KRüGER J,et al.GPGPU:general-purpose computation on graphics hardware[C]//Proceedings of ACM SIGGRAPH Course Notes.Los An-geles,USA,2004:33-41.
[40] 英伟达GPU比较表[EB/OL].[2021-09-08].https://www.nvidia.cn/studio/compare-gpus/.
[41] NVIDIA发布深度学习超级计算机DGX-1,基于Tesla P100[EB/OL].(2016-04-06) [2021-09-08].https://blog.csdn.net/happytofly/article/details/80122574.
[42] DALLY W J,GRAY C T,POULTON J,et al.Hardware-enabled artificial intelligence [C]//Proceedings of IEEE Symposium on VLSI Circuits.Honolulu,USA,2018:3-6.
[43] CHOQUETTE J,LEE E,KRASHINSKY R,et al.The A100 datacenter GPU and ampere architecture [C]// Proceedings of IEEE International Solid-State Circuits Confe-rence(ISSCC).San Francisco,USA,2021:48-49.
[44] JOUPPI N P,YOUNG C,PATIL N,et al.In-datacenter performance analysis of a tensor processing unit [C]// Proceedings of ACM/IEEE the 44th Annual International Symposium on Computer Architecture (ISCA).Toronto,Canada,2017:1-12.
[45] 谷歌第二代TPU:功耗性能究竟如何?巨头想用它干什么?[EB/OL].(201-05-23) [2021-09-08].https://tech.sina.com.cn/zl/post/detail/it/2017-05-23/pid_8511070.htm.
[46] JOUPPI N P,YOUNG C,PATIL N,et al.A domain-specific architecture for deep neural networks [J].Communications of the ACM,2018,61 (9):50-59.
[47] 李飞飞亲自宣布：Google 第三代 Cloud TPU 要来了[EB/OL].(2018-07-25) [2021-09-08].https://www.leiphone.com/category/industrynews/JBWGYS6jY2dzhVvr.html.
[48] LU T J,MARIN T,ZHUO Y,et al.Accelerating MRI reconstruction on TPUs [C]//Proceedings of IEEE High Performance Extreme Computing Conference (HPEC).Waltham,USA,2020:9286192-1-9286192-9.
[49] Google谷歌第四代定制AI芯片TPU v4 Pods整合算力及性能详解[EB/OL].(2021-05-19) [2021-09-08].https://www.eet-china.com/news/11659.html.
[50] Intel.Nervana engine delivers deep learning at ludicrous speed! [EB/OL].(2017-05-03) [2021-09-08].https://www.codeproject.com/Articles/1185288/Nervana-Engine-delivers-deep-learning-at-ludicrous.
[51] ALCORN P.10 nm ice lake CPU meets M.2:the 'Spring Hill' Nervana NNP-I deep dive[EB/OL].(2019-08-21) [2021-09-08].https://www.tomshardware.com/news/intel-10nm-ice-lake- neural-network-processor-ai-inference-m.2,40204.html.
[52] CAULFIELD A M,CHUNG E S,PUTNAM A,et al.A cloud-scale acceleration architecture [C]// Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).Taipei,China,2016:7783710-1-7783710-16.
[53] FOWERS J,OVTCHAROV K,PAPAMICHAEL M,et al.A configurable cloud-scale DNN processor for real-time AI [C]//Proceedings of ACM/IEEE the 45th Annual International Symposium on Computer Architecture (ISCA).Los Angeles,USA,2018:1-14.
[54] FLEISCHER B,SHUKLA S,ZIEGLER M,et al.A scalable multi-TeraOPS deep learning processor core for AI training and inference [C]//Proceedings of IEEE Symposium on VLSI Circuits.Honolulu,USA,2018:35-36.
[55] AGRAWAL A,LEE S K,SILBERMAN J,et al.9.1 A 7 nm 4-core AI chip with 25.6 TFLOPS hybrid fp8 trai-ning,102.4 TOPS int4 inference and workload-aware throttling [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2021:144-145.
[56] YAMAMOTO K,ANDO K,MERTIG N,et al.STATICA:a 512-spin 0.25 M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2020:138-139.
[57] JIAO Y,HAN L,JIN R,et al.7.2 A 12 nm programmable convolution-efficient neural-processing-unit chip achieving 825 TOPS[C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2020:136-137.
[58] KANG S,HAN D,LEE J,et al.GANPU:a 135 TFLOPS/W multi-DNN training processor for GANs with speculative dual-sparsity exploitation [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2020:140-141.
[59] LIN C H,CHENG C C,TSAI Y M,et al.7.1 A 3.4-to-13.3 TOPS/W 3.6 TOPS dual-core deep-learning accelerator for versatile AI applications in 7 nm 5G smartphone SoC [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2020:134-135.
[60] 科技联盟|寒武纪7 nm训练芯片思元290及玄思1000加速器正式亮相[EB/OL].(2021-02-20) [2021-09-08].https://www.sohu.com/a/451643527_100051977.
[61] MO H Y,ZHU W P,HU W J,et al.9.2 A 28 nm 12.1 TOPS/W dual-mode CNN processor using effective-weight-based convolution and error-compensation-based prediction [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2021:146-147.
[62] PARK J,LEE S,JEON D.A 40 nm 4.81 TFLOPS/W 8b floating-point training processor for non-sparse neural networks using shared exponent bias and 24-way fused multiply-add tree [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2021:148-149.
[63] OUYANG J,DU X L,MA Y,et al.Kunlun:a 14 nm high-performance AI processor for diversified workloads [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2021:50-51.
[64] MATSUBARA K,LIESKE H,KIMURA M,et al.A 12 nm autonomous-driving processor with 60.4 TOPS,13.8 TOPS/W CNN executed by task-separated ASIL D control [C]//Proceedings of IEEE International Solid- State Circuits Conference (ISSCC).San Francisco,USA,2021:56-57.
[65] PERSHIN Y V,VENTRA M D.Experimental demonstration of associative memory with memristive neural networks [J].Neural Networks,2010,23(7):881-886.
[66] GOKMEN T,ONEN M,HAENSCH W.Training deep convolutional neural networks with resistive cross-point devices [J].Frontiers in Neuroscience,2017,11:538-1-538-13.
[67] GOKMEN T,RASCH M J,HAENSCH W.Training LSTM networks with resistive cross-point devices[J].Frontiers in Neuroscience,2018,12:745-1-745-10.
[68] AMBROGIO S,NARAYANAN P,TSAI H,et al.Equi-valent-accuracy accelerated neural-network training using analogue memory [J].Nature,2018,558:60-67.
[69] ZHANG J T,WANG Z,VERMA N.A machine-learning classifier implemented in a standard 6T SRAM array [C]//Proceedings of IEEE Symposium on VLSI Circuits.Honolulu,USA,2016:7573566-1-7573566-2.
[70] JIANG Z W,YIN S H,SEOK M,et al.XNOR-SRAM:in-memory computing SRAM macro for binary/ternary deep neural networks [C]//Proceedings of IEEE IEEE Symposium on VLSI Technology.Honolulu,USA,2018:173-174.
[71] GUO R Q,LIU Y G,ZHENG S X,et al.A 5.1 pJ/neuron 127.3 μs/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65 nm CMOS [C]//Proceedings of IEEE Symposium on VLSI Circuits.Kyoto,Japan,2019:120-121.
[72] OKUMURA S,YABUUCHI M,HIJIOKA K,et al.A ternary based bit scalable,8.80 TOPS/W CNN accelerator with many-core processing-in-memory architecture with 896 k synapses/mm2 [C]//Proceedings of Symposium on VLSI Technology.Kyoto,Japan,2019:248-249.
[73] DONG Q,SINANGIL M E,ERBAGCI B,et al.15.3 A 351 TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2020:242-243.
[74] YUE J S,YUAN Z,FENG X Y.14.3 A 65 nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity perfor-mance-scaling architecture and energy-efficient inter/intra-macro data reuse [C]//Proceedings of IEEE International Solid-State Circuits Conference.San Francisco,USA,2020:234-235.
[75] SU J W,SI X,CHOU Y C,et al.15.2 A 28 nm 64 kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips [C]//Proceedings of IEEE International Solid- State Circuits Conference (ISSCC).San Francisco,USA,2020:240-241.
[76] GUO R Q,YUE Z H,SI X,et al.15.4 A 5.99-to-691.1 TOPS/W tensor-train in-memory-computing processor using bit-level-sparsity-based optimization and variable-precision quantization [C]//Proceedings of IEEE International Solid- State Circuits Conference (ISSCC).San Francisco,USA,2021:242-243.
[77] YUE J S,FENG X Y,HE Y F,et al.15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC) .San Francisco,USA,2021:238-239.
[78] CHEN Z Y,CHEN X,GU J.15.3 A 65 nm 3T dynamic analog RAM-based computing-in-memory macro and CNN accelerator with retention enhancement,adaptive analog sparsity and 44 TOPS/W system energy efficiency [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2021:240-241.
[79] le GALLO M,SEBASTIAN A,MATHIS R,et al.Mixed-precision in-memory computing [J].Nature Electronics,2018,1:246-253.
[80] CHEN W H,LI K X,LIN W Y,et al.A 65 nm 1 Mb nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2018:494-495.
[81] MOCHIDA R,KOUNO K,HAYATA Y,et al.A 4M synapses integrated analog ReRAM based 66.5 TOPS/W neural-network processor with cell current controlled writing and flexible network architecture [C]//Proceedings of IEEE Symposium on VLSI Technology.Honolulu,USA,2018:175-176.
[82] SEBASTIAN A,BOYBAT I,DAZZI M,et al.Computational memory-based inference and training of deep neural networks [C]//Proceedings of Symposium on VLSI Technology.Kyoto,Japan,2019:168-169.
[83] XUE C X,CHEN W H,LIU J S,et al.24.1 A 1 Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN-based AI edge processors [C]//Proceedings of IEEE International Solid- State Circuits Conference (ISSCC).San Francisco,USA,2019:388-389.
[84] XUE C X,HUANG T Y,LIU J S,et al.A 22 nm 2 Mb ReRAM compute-in-memory macro with 121-28 TOPS/W for multibit MAC computing for tiny AI edge devices[C]//Proceedings of IEEE International Solid- State Circuits Conference (ISSCC).San Francisco,USA,2020:244-245.
[85] LIU Q,GAO B,YAO P,et al.33.2 A fully integrated analog ReRAM based 78.4 TOPS/W compute-in-memory chip with fully parallel MAC computing[C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2020:500-501.
[86] XUE C X,HUNG J M,KAO H Y,et al.16.1 A 22 nm 4 Mb 8 b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices [C]//Proceedings of IEEE International Solid-State Circuits Conference (ISSCC).San Francisco,USA,2021:246-247.
[87] YOON J H,CHANG M,KHWA W S,et al.A 40 nm 100 kb 118.44 TOPS/W ternary-weight compute-in-memory RRAM macro with voltage-sensing read and write verification for reliable multi-bit RRAM operation [C]//Procee-dings of IEEE Custom Integrated Circuits Conference (CICC).Austin,USA,2021:9431412-1-9431412-2.
基本信息:
DOI：10.13250/j.cnki.wndz.2022.04.001
中图分类号:TN386;TN40;TP18
引用信息:
[1]赵正平.FinFET/GAAFET纳电子学与人工智能芯片的新进展(续)[J].微纳电子技术,2022,59(04):293-305.DOI:10.13250/j.cnki.wndz.2022.04.001.
2022-04-06
2022-04-06