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随着图形特征尺寸的不断缩小、集成度的不断提高,集成电路已进入纳米系统芯片(SOC)阶段,摩尔定律依靠器件尺寸缩小得以延续的方式正面临着众多挑战。分析了纳米SOC中影响性能和良品率的关键效应及相应的措施。从半导体产业链的发展演变指出了可制造性设计(DFM)是纳米SOC阶段提高可制造性与良品率的解决方案。与光刻性能相关的分辨率增强技术(RET)是推动DFM发展的第一波浪潮,下一代的DFM将更注重良品率的受限分析及设计规则的综合优化。综述了DFM产生的历史及发展的现状,并对其前景进行了展望。
Abstract：With the continuous scaling down of feature dimension,IC industry has entered the era of nano-SOC. Moore's Law,which depends on the scaling down of device dimension,is fa-cing many challenges. The key effects are analyzed,which influence the performance and yield of nano-SOC. The corresponding measures are also explained. It can be concluded from the development and change of semiconductor industry chain that the design for manufacturability(DFM)can improve the manufacturability and yield in nano-SOC era. The resolution enhancement techniques(RET)relating lithography performance drove the foremost development of DFM. The next generation DFM will pay more attention to yield,rule synthesis and optimization. The history and status of DFM are presented,and the future of it is also prospected.
[1]李志坚,周润德.ULSI器件、电路、系统[M].北京:科学出版社,2000.
[2]翁寿松.光刻、OPC与DFM[J].电子工业专用设备,2006,35(4):18-22.
[3]PETERS L.DFM:碰撞然后合作的世界[EB/OL].[2005-12-27].http://www.sichinamag.com/Article/html/2005-12/20051227054523.htm.
[4]王国雄,严晓浪,史峥,等.基于模型的光学校正系统的设计与实现[J].浙江大学学报(工学版),2004,38(5):521-524.
[5]崔铮.微纳米加工技术及其应用[M].北京:高等教育出版社,2005.
[6]陆晶,陈宝钦,刘明,等.100nm分辨率交替式移相掩模设计[J].固体电子学研究与进展,2005,25(2):260-264.
[7]FRANK D J,DENNARD R H,NOWAK E,et al.Device scaling limits of Si MOSFETs and their application dependen-cies[J].Proc IEEE,2001,89(3):280.
[8]李志坚,李铁夫.浅谈后摩尔定律时期微电子技术的发展[EB/OL].[2005-02].http://www.cicmag.com/0502rdts02.asp.
[9]PETERS L.45nm技术的选择[EB/OL].[2006-03-15].http://www.sichinamag.com/Article/html/2006315025726.htm.
[10]SINGER P.45nm新材料面临的风险和回报[EB/OL].(2005-03)[2006-11-21].http://www.sichinamag.com/Arti-cle/html/2006112143051d5ac2.htm.
[11]SINGER P.新工艺减少栅泄漏[EB/OL].[2006-05-11].http://www.sichinamag.com/Article/html/2006511011718.htm.
[12]ALTERA.65nm半导体工艺发展策略[EB/OL].http://www.cednt.cn/element/14805.html.
[13]仲佳明.Post-layout分析应对纳米设计挑战[EB/OL].http://www.eetchina.com/ARTP_8800306065_480401.htm.
[14]MILLER M,THON D.可制造性设计对90nm以下设计流程的影响[EB/OL].http://www.eetchina.com/artp_8800399403_480201.htm.
[15]史峥,沈珊瑚,严晓浪.来自亚100nm可制造性的挑战[J].计算机世界报,2005(43):B8-B9.
[16]SCHELLENBERG F M.Sub-wavelength lithography using OPC[J].Semiconductor Fabtech,1999(9):205-207.
[17]PETERS L.DFM透视[J].半导体国际(中文版),2005,1(5):18.
[18]SANTARINI M.对DFM选手过筛[EB/OL].[2006-11-01].http://article.ednchina.com/eda/20061101072738.htm.
[19]王彦.DFM是半导体厂商所面临的最大挑战[EB/OL].http://www.eetchina.com/art_8800436345.htm.
[20]PETERS L.TSMC和UMC推出不同的65nm DFM解决方案[EB/OL].[2006-10-14].http://www.sichinamag.com/arti-cle/html/20061014074335.htm.
[21]新思推出PA-DFM方案.挑战45nm制程[EB/OL].[2006-10-19].http://www.sichinamag.com/article/html/20061019032548.htm.
[22]张国勇.面临双重压力,领先代工厂扮演设计新角色[EB/OL].http://www.ed-china.com/art_8800013728_400012_500016_OT_14E82237.htm.
基本信息:
中图分类号:TN47
引用信息:
[1]赵珉,杨清华,刘明,等.可制造性设计在纳米SOC中的应用和发展[J].微纳电子技术,2007,No.361(06):282-288.
基金信息:
国家自然科学基金资助项目(60676001,60676008)
2007-06-15
2007-06-15